• Multisynth-based Architecture

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    July 22, 2017 /  Architecture
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    Traditional clock generators use a simple integer-N phased-locked loop (PLL)-based architecture. The output clock frequency is a function of the input clock frequency and the PLL divider values as shown in the equation
    Equation: fOUT = fIN.N/P.R
    Traditional single PLL-based IC solutions are suitable for simple integer clock multiplication of reference inputs or clock generation from crystal inputs. However, many applications require clock generation of multiple non-integer-related frequencies (e.g., 125 MHz Ethernet and 106.25llMHz Fibre Channel). Traditional solutions require that the crystal frequency be changed to support each unique frequency plan. This forces the designer to use one or more custom crystals and multiple clock generator ICs to generate the required set of frequencies, increasing the cost, complexity and power consumption of the overall solution.

    New Any-Rate Clock Multiplier Architecture Simplifies Design
    Recent advances in mixed-signal analog design have made it possible to provide any-rate frequency synthesis from a single device. Silicon Labs newest clock architecture leverages a fractional-N PLL used in concert with a low-jitter fractional divider termed MultiSynth to produce any-rate frequency synthesis on multiple output clocks. The flagship of this new product family is the Si5338 Any-Rate, Any-Output Quad Clock Generator. This technology dramatically simplifies timing architectures by integrating the frequency synthesis capability of four PLLs in a single device, greatly reducing size and power requirements compared to traditional solutions.

    MultiSynth Technology
    The Si5338s low phase noise, high-frequency VCO supplies a high-frequency output clock to the MultiSynth block on each of the four independent output paths. The first stage of the MultiSynth architecture is a fractional-N divider, which switches seamlessly between the two closest integer divider values to produce the exact output clock frequency with 0 ppm error. To eliminate phase error generated by this process, the MultiSynth calculates the relative phase difference between the clock produced by the fractional-N divider and the desired output clock and dynamically adjusts the phase to match the ideal clock waveform. This novel approach makes it possible to generate any output clock frequency without sacrificing jitter performance. Based on this architecture, each output clock can be individually programmed to generate any frequency from 0.16 to 350 MHz, and select frequencies to 700 MHz. Typical jitter performance enabled by this MultiSynth-based architecture is 1 ps RMS.

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